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The Xeon brand refers to many families of Intel's x86 multiprocessing CPUs – for dual-processor (DP) and multi-processor (MP) configuration on a single motherboard targeted at non-consumer markets of server and workstation computers, and also at blade servers and embedded systems. The Xeon brand has been maintained over several generations of x86 and x86-64 processors. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, but more recent models used the name Xeon on its own. The Xeon CPUs generally have more cache than their desktop counterparts in addition to multiprocessing capabilities. Intel's (non-x86) IA-64 processors are called Itanium, not Xeon.

Pentium II Xeon

The first Xeon branded processor was released in 1998, named the Pentium II Xeon (codenamed "Drake"), as the replacement of the Pentium Pro. It was based on the 0.25 µm "Deschutes" core (P6 microarchitecture) branded Pentium II (sharing its 80523 product code), used either a 440GX (a dual-processor workstation chipset) or 450NX (quad-processor, or oct with additional logic) chipset, and differed from the Pentium II desktop CPU (Deschutes) in that its off-die L2 cache ran at full speed. It also used a larger slot known as slot 2. Cache sizes were 512 KB, 1 MB, and 2 MB, and it used a 100 MT/s front side bus (FSB).

Pentium III Xeon

In 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. Reflecting the incremental changes from the Pentium II "Deschutes" core to the Pentium III "Katmai" core, the first Pentium III Xeon, named "Tanner", was just like its predecessor except for the addition of Streaming SIMD Extensions (SSE) and a few cache controller improvements. The second version, named "Cascades", was based on the Pentium III "Coppermine" core. The "Cascades" Xeon used a 133 MT/s bus and relatively small 256 KB on-die L2 cache resulting in almost the same capabilities as the Slot 1 Coppermine processors, which were capable of dual-processor operation but not quad-processor operation. To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. Product codes for Tanner and Cascades mirrored that of Katmai and Coppermine; 80525 and 80526 respectively.

Xeon (DP) & Xeon MP (32-bit)

Foster

In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new NetBurst architecture, "Foster", was slightly different from the desktop Pentium 4 ("Willamette"). It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascades 2 MB core and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive.

At most two Foster processors could be accommodated in a symmetric multiprocessing (SMP) system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MB L3 cache and the Jackson Hyper-Threading capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The Foster shared the 80528 product code with Willamette.

Prestonia

In 2002 Intel released a 130 nm version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 KB L2 cache. This was based on the "Northwood" Pentium 4 core. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM) was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.

Gallatin

Subsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version also performed much better than the Foster MP, and was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache. The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood.

Xeon (DP) & Xeon MP (64-bit)

Due to a lack of success with Intel's Itanium and Itanium 2 processors, AMD was able to introduce x86-64, a 64-bit extension to the x86 architecture. Intel followed suit by including Intel 64 (formerly EM64T; it is almost identical to AMD64) in the 90 nm version of the Pentium 4 ("Prescott"), and a Xeon version codenamed "Nocona" was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.

A slightly updated core called "Irwindale" was released in early 2005, with twice the L2 cache of Nocona and able to reduce its clockspeeds during low processor demand. However, independent tests showed that AMD's Opteron still outperformed Irwindale.

64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. All these Prescott-derived Xeons have the product code 80546.

Dual-Core Xeon

"Paxville DP"

The first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on 10 October 2005. Paxville DP had NetBurst architecture, and was a dual-core equivalent of the single-core Irwindale (related to the Pentium D branded "Smithfield"") with 4 MB of L2 Cache (2 MB per core). The only one Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process.

7000-series "Paxville MP"

An MP-capable version of Paxville DP, codenamed Paxville MP, product code 80560, was released on 1 November 2005. There are two versions: one with 2 MB of L2 Cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 GHz and 3.0 GHz (model numbers 7020-7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.

LV (ULV), "Sossaman"

On 14 March 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage). Subsequently an ULV (ultra-low-voltage) version was released. The Sossaman was a low-/ultra-low-power and double-processor capable CPU (like AMD Quad FX), based on the "Yonah" processor, for ultradense non-consumer environment (i.e. targeted at the blade-server and embedded markets), and it was rated at a thermal design power (TDP) of 31 W (LV: 1.66 GHz and 2 GHz ) and 15 W (ULV: 1.66 GHz)[2]. As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but it did not support 64-bit operations, so it could not run 64-bit-only server software, such as Microsoft Exchange Server 2007, and therefore it was limited to only 16 GB of memory. A planned successor, codenamed "Merom MP" was to be a drop-in upgrade to allow Sossaman-based servers to upgrade to 64-bit capability. However, this was abandoned in favour of low-voltage versions of the Woodcrest LV processor leaving the Sossaman at a dead-end with no planned upgrades.

5000-series "Dempsey"

On 23 May 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst architecture processor produced using a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50 GHz and 3.73 GHz (model numbers 5020-5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 Cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: Socket J, also known as LGA 771.

5100-series "Woodcrest"

On 26 June 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed Woodcrest (product code 80556); it was the first Intel Core microarchitecture processor to be launched on the market. It is a server and workstation version of the Intel Core 2 processor. Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.

Most models have a 1333 MT/s FSB, except for the 5110 and 5120, which have a 1066 MT/s FSB. The fastest processor (5160) operates at 3.0 GHz. All Woodcrests use LGA 771 and all except two models have a TDP of 65 W. The 5160 has a TDP of 80 W and the 5148LV (2.33 GHz) has a TDP of 40 W. The previous generation Xeons had a TDP of 130 W. All models support Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, with the "Demand Based Switching" power management option only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MB of shared L2 Cache.

7100-series "Tulsa"

Released on 29 August 2006,[3] the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MB of L2 cache (1 MB per core) and up to 16 MB of L3 cache. It uses Socket 604 . Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 GHz to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 GHz to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MB to 16 MB across the models.

7200-series "Tigerton"

The 7200 series, codenamed Tigerton (product code 80564) is an MP-capable processor, similar to the 7300 series, but, in contrast, only one core is active on each silicon chip, and the other one is turned off (blocked), resulting as a dual-core capable processor.

3000-series "Conroe"

The 3000 series, codenamed Conroe (product code 80557) dual-core Xeon (branded) CPU, released at the end of September 2006, was just a rebranded version of the Intel's mainstream Conroe, otherwise branded as Core 2 Duo (for consumer desktops). Unlike most Xeon processors, they only supported single-CPU operation. They use Socket T (LGA775), operate on a 1066 MHz front-side bus, support Enhanced Intel Speedstep Technology and Intel Virtualization Technology but do not support Hyper-Threading. Intel Processors with a number ending in "5" have a 1333 MT/s FSB.

3100-series "Wolfdale"

The 3100 series, codenamed Wolfdale (product code 80570) dual-core Xeon (branded) CPU, was just rebranded version of the Intel's mainstream Wolfdale featuring the same 45 nm process and 6 MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They use Socket T (LGA775), operate on a 1333 MHz front-side bus, support Enhanced Intel Speedstep Technology and Intel Virtualization Technology but do not support Hyper-Threading.

5200-series "Wolfdale DP"

On 11 November 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed Wolfdale DP (product code 80573), it is built on a 45 nm process like the desktop Core 2 Duo Wolfdale and the Xeon-SP Wolfdale, featuring Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, it is unclear whether the "Demand Based Switching" power management will be available on the L5238 which is scheduled for April 2008. Wolfdale has 6 MB of shared L2 Cache.

Quad-Core and Multi-Core Xeon

3200-series "Kentsfield"

Intel released relabeled versions of its quad-core (2x2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on 7 January 2007. The 2x2 "quad-core" (dual-die dual-core) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2.13 GHz, 2.4 GHz and 2.66 GHz, respectively. Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MHz front-side bus. It is targeted at the "blade" market. The X3220 is also branded and sold as Core2 Quad Q6600, the X3230 as Q6700.

3300-series "Yorkfield"

Intel released relabeled versions of its quad-core (2x2) Core 2 Quad Yorkfield Q9400 and Q9x50 processors as the Xeon 3300-series (product code 80569). It comprised two separate dual-core dies next to each other in one CPU package and manufactured in a 45 nm process. The models are the X3320, X3350, X3360 and X3370, running at 2.50 GHz, 2.66 GHz, 2.83 GHz and 3.0 GHz, respectively. The L2 cache is a unified 6 MB per die (except for the X3320 with a smaller 3 MB L2 cache per die), and a front-side bus of 1333 MHz. All models feature Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, as well as "Demand Based Switching".

5300-series "Clovertown"

A quad-core (2x2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-core Kentsfield. The Clovertown has been usually implemented with two Woodcrest dies on a multi-chip module, with 8 MB of L2 cache (4 MB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released Clovertown, product code 80563, on 14 November 2006[ with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 GHz to 2.66 GHz. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB. All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310, L5320 and L5335 (1.6 GHz, 1.86 GHz and 2.0 GHz respectively). The 3.0 GHz X5365 arrived in July 2007, and became available in the Apple Mac Pro on 4 April 2007. The X5365 is among the fastest processors, performing up to around 38 GFLOPS in the LINPACK benchmark.

5400-series "Harpertown"

On 11 November 2007 Intel presented Yorkfield based Xeons - called Harpertown (product code 80574) - to the public.[9] This family consists of dual die quad-core CPUs manufactured on a 45 nm process and featuring 1333 MHz to 1600 MHz front-side buses, with TDP rated from 50 W to 150 W depending on the model. These processors fit in the LGA771 socket. All models feature Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, as well as the Demand Based Switching, except the E5405, which lacks this feature. The supplementary character in front of the model-number represents the thermal rating: an L depicts an TDP of 50 W, an E depicts 80 W whereas a X is 120 W TDP or above. The speed of 3.00 GHz comes as four models, two models with 80 W TDP two other models with 120 W TDP with 1333 MHz or 1600 MHz front-side bus respectively. The fastest Harpertown is the X5492 whose TDP of 150 W is higher than those of the Prescott-based Xeon DP but having twice as many cores. (The X5482 is also sold under the name "Core 2 Extreme QX9775" for use in the Intel SkullTrail system.)

Intel 1600 MHz front-side bus Xeon processors will drop into the Seaburg chipset whereas several mainboards featuring the Intel 5000/5200-chipset are enabled to run the processors with 1333 MHz front-side bus processors. Seaburg features support for dual PCIe 2.0 x16 slots and up to 128 GB of memory.

7300-series "Tigerton"

The 7300 series, codenamed Tigerton (product code 80565) is a four-socket (packaged in Socket 604) and greater capable quad-core processor, consisting of two dual core Core2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules. It was announced on 5 September 2007 , and is currently shipping.

The 7300 series uses Intel's Caneland (Clarksboro) platform.

Intel claims the 7300 series Xeons offer more than twice the performance and more than three times the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor.

The 7xxx series is aimed at the large server market, supporting configurations of up to 32 CPUs per host.

7400-series "Dunnington"

Dunnington - the last CPU of the Penryn generation and Intel's first multi-core (above two) die - features a single-die six- (or hexa-) core design with three unified 3 MB L2 caches (resembling three merged 45 nm dual-core Wolfdale dies), and 96 KB L1 cache (Data) and 16 MB of L3 cache. It features 1066 MHz FSB, fits into the Tigerton's mPGA604 socket, and is compatible with the Caneland chipset. These processors support DDR2-1066 (533 MHz), and have a maximum TDP below 130 W. They are intended for blades and other stacked computer systems. Availability is scheduled for the second half of 2008. It will be followed shortly by the Nehalem microarchitecture.

Announced on Sept. 15, 2008. Intel link

5500-series "Gainestown"

Gainestown is the codename for the successor to the Xeon Intel Core microarchitecture, is based on the Nehalem architecture and uses the same 45 nm manufacturing methods as Intel's Penryn. The first processor released with the Nehalem architecture is the desktop Core i7, which was released in November 2008. Server processors of the Xeon 55xx range were first supplied to testers in December 2008.

The performance improvements over previous Xeon processors are based mainly on:

* Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM channels
* A new point-to-point processor interconnect QuickPath, replacing the legacy front side bus
* Simultaneous multithreading by multiple cores and hyperthreading (2x per core).