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The Intel i486, otherwise known as the 80486, was the first tightly pipelined x86 design. Introduced in 1989, it was also the first x86 chip to use more than a million transistors, due to a large on-chip cache and an integrated floating point unit. It represents a fourth generation of binary compatible CPUs since the original 8086 of 1978, and it was the second 32-bit x86 design after the 80386.

A 50 MHz 80486 was reportedly able to perform 41 million instructions per second and was able to reach 50 MIPS peak.

(The i486 was so named, without the usual 80-prefix, because of a court ruling that prohibited trademarking numbers like 80486. Later, with the Pentium, Intel dropped number-based naming altogether.)

Improvements

The instruction set of the i486 is very similar to its predecessor, the Intel 80386, with the addition of only a few extra instructions, such as CMPXCHG which executes the Compare-and-swap atomic operation and the XADD which executes the Fetch-and-add atomic operation. Though many atomic test-and-set instructions have existed since the 8086/8088, they did not correspond to the atomic instructions implemented in certain RISC processors, which made it harder to port some applications from these processors.

From a performance point of view, the architecture of the i486 is a vast improvement over the 80386. It has an on-chip unified instruction and data cache, an on-chip floating-point unit (FPU), and an enhanced bus interface unit. In addition, simple instructions (such as ALU reg,reg) execute in one clock cycle. These improvements yield a rough doubling in performance over the 386 at the same clock rate. A 386 (or 286) chip therefore has to reach 50 MHz to be comparable with low end parts in the 486 series.
The 486DX2 architecture.

Differences between the 386 and 486

* An 8 KB on-chip SRAM cache stores the most commonly used instructions and data (16 KB and/or write-back on some later models). The 386 had no such internal cache but supported a slower off-chip cache.
* Tightly coupled pipelining allows the 486 to complete a simple instruction like ALU reg,reg or ALU reg,im every clock cycle. The 386 needed two clock cycles for this.
* Integrated FPU (disabled or absent in SX models) with a dedicated local bus gives faster floating point calculations compared to the i386+i387 combination.
* Improved MMU performance.

The 486 has a 32-bit data bus and a 32-bit address bus. This required either four matched 30-pin (8-bit) SIMMs or one 72-pin (32-bit) SIMM on a typical PC motherboard. The 32-bit address bus means that 4 GB of memory can be directly addressed.

The Intel project manager for the 80486 was Pat Gelsinger.

In May 2006 Intel announced that production of the 80486 would cease at the end of September 2007. Although the chip had long been obsolete for personal computer applications, Intel had continued production for use in embedded systems.